Volantis raises $88 million to attack AI’s memory wall with light

The story

Volantis has raised an $88 million Series A to develop a photonic connection between artificial-intelligence processors and large pools of memory, aiming at one of the most persistent limits on advanced inference systems. The round was led by investor Lachy Groom and Abstract Ventures and brings the semiconductor startup’s disclosed funding to $97 million. Reuters independently reported the financing on October 1, while the company has described its architecture and launch targets in a technical announcement.

The problem Volantis calls the memory wall is straightforward even if the engineering is not. Large models must repeatedly move weights, attention data and cached context between memory and compute. A processor may have abundant arithmetic capacity, yet spend valuable time waiting for data. High-bandwidth memory, or HBM, reduces that delay by placing fast memory stacks close to an accelerator, but physical space, electrical reach, power and packaging complexity restrict how many stacks can be attached.

Volantis proposes replacing part of that short electrical path with light. Its interconnect uses integrated micro-VCSELs — vertical-cavity surface-emitting lasers — to transmit data between compute and memory chiplets. Unlike an optical-computing chip, the design does not use photons to perform the model’s matrix calculations. Light is the transport layer: the processor still computes electronically, while the optical fabric is intended to move data farther and at greater aggregate bandwidth.

VCSELs emit light perpendicular to the surface of a semiconductor wafer and can be fabricated in dense arrays. The devices are already used at large scale in sensing applications, including consumer depth systems. Volantis argues that integrating small VCSELs with its interconnect removes the external lasers and conventional fibre normally associated with optical networking, creating a link that can be packaged more like a semiconductor component. That integration is central to the company’s cost and reliability thesis, but it has not yet been demonstrated in a shipping product.

The proposed scale is ambitious. Volantis says its optical reach could let one processor connect to more than 220 memory chiplets in a uniform-latency pool, compared with the much smaller number of HBM stacks placed beside current accelerators. The company describes an A-1 inference appliance with 10 terabytes of memory and 250 terabits per second of bandwidth. It also targets models above 20 trillion parameters and throughput of as much as 10,000 tokens per second for one user.

Those figures should be read as company targets, not established benchmark results. Volantis has not released third-party tests, detailed workload settings, latency distributions, power consumption or silicon yield. Token throughput in particular depends on model architecture, numerical precision, batching, context length and software, so it cannot be compared meaningfully without a reproducible test. The funding validates investor interest and gives the company resources to build; it does not validate the advertised performance.

The investor group nevertheless signals how seriously the bottleneck is being treated. In addition to Groom and Abstract, Volantis named Kleiner Perkins chair John Doerr, VXI Capital, Triatomic Capital, Susa Ventures and several technology executives and researchers. The startup says its team includes veterans of Nvidia, AMD, Broadcom and Ayar Labs. Reuters reported that Volantis expects to ship its chip in 2027, making execution over the next year more consequential than another set of simulations.

INNOVOX analysis: the significance of Volantis is not that it has already displaced HBM or conventional scale-up links. It is that AI infrastructure investment is moving from raw accelerator count toward the movement of data around those accelerators. As models and context windows grow, memory capacity and bandwidth can determine whether expensive compute is productive. A credible optical memory fabric could allow system designers to separate memory capacity from the tight perimeter of a processor package and share larger pools more efficiently.

The architecture also introduces new risks. Lasers, detectors, control circuits and memory must be aligned and packaged with high yield. Optical reach is useful only if latency stays predictable, the error rate is manageable and energy per transferred bit remains competitive. Software must treat the larger pool intelligently, and data-centre operators will care about serviceability as much as a peak bandwidth figure. Meanwhile, HBM and electrical interconnect standards will continue improving rather than stand still.

What to watch next is evidence from real silicon. Named foundry, packaging and memory partners would make the manufacturing path clearer. Customer evaluations would show whether the system fits existing inference software and data-centre operations. Most important will be independently reproducible comparisons covering bandwidth, latency, energy, reliability and total cost on the same model. If Volantis can substantiate even a meaningful portion of its claims at production scale, photonics could become a practical way to feed AI processors rather than merely connect racks.

INNOVOX analysis

Volantis is addressing a genuine constraint: an expensive AI processor is underused when model weights and cached data cannot reach it quickly enough. Moving that traffic optically could expand memory capacity without simply packing more high-bandwidth-memory stacks next to every accelerator. The investment is a serious vote of confidence, but the commercial case will depend on manufacturability, software integration and verified performance rather than headline bandwidth alone.

What to watch

Watch for first silicon, named manufacturing and packaging partners, customer evaluations, and reproducible measurements for bandwidth, latency, energy per bit and yield. The decisive comparison will be against improving HBM systems and other scale-up interconnects under the same inference workload.